Careers

We are a friendly, hard-working and helpful team of technology experts delivering embedded system solutions, specializing in programmable media networking.

Our goal is to unite the best people into a focused, specialist technology firm; one positioned to ensure our customer’s success while your career moves forward, as you learn the latest technologies, tools and processes, while working in a supportive and dynamic environment.

Current Positions

The following positions are presently open in our various offices across Canada.  If you feel you would be a great addition to our team and think you have the right skills, we will always be pleased to review your credentials and career plan.

FPGA or ASIC Verification Designer (Ottawa & Toronto)

This job might be for you if:
You want your contributions to make a noticeable impact. You love taking on difficult challenges and the satisfaction that comes from finding creative solutions. If you don’t know the answer, you’ll dig until you find it. You play nice with humans and machines. You think on your feet. You like learning new things, and you can learn quickly. You can explain just about anything to anyone. You’re going to take ownership of the time you spend with us and truly make a difference.

A typical day might include:
– Read up on a new standard to understand the system’s desired behavior
– Create a new UVM component in SystemVerilog to model the behavior of a packet source
– Connect the component in the testbench and write a new testcase to cover a feature
– Update the testbench design spec
– Update the verification plan with the testcase result
– Work with project management to track progress
– Run a regression and check the system functional coverage
– Work with the RTL designer to debug a failing testcase
– Improve a script for automatic register generation
– Push the changes in GIT and tag a new release
– Work with software and RTL designers in the lab to get a device running
– Run some tests to characterize the maximum DMA bandwidth
– Update Redmine with the progress made on current tasks

You have:
– Knowledge of SystemVerilog and UVM
– Expertise in SoC FPGA interconnects such as Avalon or AXI4 interfaces
– Experience with Modelsim, VCS, Altera Quartus or Xilinx Vivado Tools
– Familiarity with FPGA workflows including RTL design and synthesis
– Expertise in RTL debugging through waveform simulations and self-checking testbenches
– Familiarity with hardware integration and lab tools

You might also have:
– Knowledge of VMM, OVM, Specman or VERA
– Experience with ARM multi-processor systems within an embedded Linux environment
– Knowledge of PCI Express, Ethernet, 10GE, and other protocols

Lead Embedded Software Designer

This job might be for you if:
You want your contributions to make a noticeable impact. You love taking on difficult challenges and the satisfaction that comes from finding creative solutions. If you don’t know the answer, you’ll dig until you find it. You play nice with humans and machines. You think on your feet. You like learning new things, and you can learn quickly. You can explain just about anything to anyone. You’re going to take ownership of the time you spend with us and truly make a difference.

A typical day might include:
– Architect a solution to satisfy project requirements
– Write and review a design spec
– Work with project management to break down the design into tasks and effort estimates
– Configure the descriptor chain for an SGDMA to move Audio from Ethernet streams to DDR
– Post timestamps from hardware to a gPTP module through a Linux Ethernet driver
– Work with the hardware designer to resolve a timestamp FIFO overflow issue
– Influence the architecture and contribute to the development of the OpenAVB project
– Test then push your changes into GIT and tag a new release
– Present a proposal to improve our continuous integration flow at one of our lunch-and-learn sessions – Review the latest register definition header file from the RTL designer and update your code
– Meet with software and RTL designers to propose a lab integration strategy
– Spend some time in the lab teaching a co-op how to analyze network packets with wireshark
– Explain the interrupt strategy to an FPGA designer; ensure it meets our system requirements
– Update Redmine with the progress made on current tasks

You have:
– Experience with ARM multi-processor systems within an embedded Linux environment
– Knowledge of software design for embedded systems with a mix of application, library and driver development – Expertise in C/C++ and cross-platform programming
– Ability to resolve memory leaks and deadlocks
– Knowledge of creating hardware stubs for simulated testing
– Performed static code analysis
– Knowledge of revision control systems, branching and tagging methodologies
– Expertise in software debugging through JTAG interfaces and logic analyzers
– Familiarity with hardware integration and lab tools

You might also have:
– Expertise in SoC FPGA interconnects such as AXI4 interfaces
– Knowledge of PCI Express, OTN, Ethernet, 10GE, 3G-SDI, and other protocols
– Knowledge of media distribution standards like gStreamer, gPTP, IEEE1722, AVB/AVTP, AES67 – Knowledge of Audio (MADI, AES, I2S) and Video (4k, h.264) standards
– Familiarity with Timing recovery / Synchronization / PTP
– Understanding of DMA engines, SGDMA, high-performance memory

Lead FPGA Designer

This job might be for you if:
You want your contributions to make a noticeable impact. You love taking on difficult challenges and the satisfaction that comes from finding creative solutions. If you don’t know the answer, you’ll dig until you find it. You play nice with humans and machines. You think on your feet. You like learning new things, and you can learn quickly. You can explain just about anything to anyone. You’re going to take ownership of the time you spend with us and truly make a difference.

– A typical day might include:
– Architect a solution to satisfy project requirements
– Write and review a design spec
– Work with project management to break down the design into tasks and effort estimates
– Code a re-usable FPGA block that combines two video streams
– Connect the core to a DMA engine and high speed AXI interface
– Run the latest SystemVerilog (UVM) simulations
– Work with the verification designer to debug a failing testcase
– Synthesize the design and ensure it meets timing
– Improve a script for automatic register generation
– Push the changes in GIT and tag a new release
– Help improve our continuous-integration flow
– Meet with software and RTL designers to propose a lab integration strategy
– Spend some time in the lab teaching a co-op how to program a board
– Explain the FPGA interrupt configuration to a software designer; understand how to meet their needs – Update Redmine with the progress made on current tasks

You have:
– In-depth knowledge of Verilog or VHDL RTL
– Experience with Altera Quartus QSYS or Xilinx Vivado IPI tools
– Expertise in FPGA workflows including RTL design, synthesis, timing closure, prototyping and release – Knowledge of revision control systems, branching and tagging methodologies
– Expertise in RTL debugging through simulations and in-FPGA logic analyzers
– Familiarity with hardware integration and lab tools

You might also have:
– Expertise in SoC FPGA interconnects such as Avalon or AXI4 interfaces
– Experience with ARM multi-processor systems within an embedded Linux environment
– Knowledge of PCI Express, OTN, Ethernet, 10GE, 3G-SDI, and other protocols
– Knowledge of AVB/AVTP, AES67, Audio (MADI, AES, I2S) and Video (4k, h.264) standards
– Familiarity with Timing recovery / Synchronization / PTP
– Understanding of High-speed transceivers, DMA engines, high-performance memory controllers

Lead Verification Designer

This job might be for you if:
– You want your contributions to make a noticeable impact. You love taking on difficult challenges and the satisfaction that comes from finding -creative solutions. If you don’t know the answer, you’ll dig until you find it. You play nice with humans and machines. You think on your feet. You like learning new things, and you can learn quickly. You can explain just about anything to anyone. You’re going to take ownership of the time you spend with us and truly make a difference.

A typical day might include:
– Read up on a new standard to understand the system’s desired behavior
– Create a new UVM component in SystemVerilog to model the behavior of a packet source – Connect the component in the testbench and write a new testcase to cover a feature
– Update the testbench design spec
– Update the verification plan with the testcase result
– Work with project management to track progress
– Run a regression and check the system functional coverage
– Work with the RTL designer to debug a failing testcase
– Improve a script for automatic register generation
– Push the changes in GIT and tag a new release
– Work with software and RTL designers in the lab to get a device running
– Run some tests to characterize the maximum DMA bandwidth
– Update Redmine with the progress made on current tasks

You have:
– Knowledge of SystemVerilog and UVM
– Expertise in SoC FPGA interconnects such as Avalon or AXI4 interfaces
– Experience with Modelsim, VCS, Altera Quartus or Xilinx Vivado Tools
– Familiarity with FPGA workflows including RTL design and synthesis
– Expertise in RTL debugging through waveform simulations and self-checking testbenches – Familiarity with hardware integration and lab tools
– You might also have:
– Knowledge of VMM, OVM, Specman or VERA
– Experience with ARM multi-processor systems within an embedded Linux environment – Knowledge of PCI Express, Ethernet, 10GE, and other protocols

Junior FPGA Designer (Co-op Placement)

This job might be for you if:
You want your contributions to make a noticeable impact. You love taking on difficult challenges and the satisfaction that comes from finding creative solutions. If you don’t know the answer, you’ll dig until you find it. You play nice with humans and machines. You think on your feet. You like learning new things, and you can learn quickly. You can explain just about anything to anyone. You’re going to take ownership of the time you spend with us and truly make a difference.

A typical day might include:
– Read up on a new standard to understand the system’s desired behavior
– Review a block of RTL and add a new feature to it
– Update a design spec
– Work with project management to track progress
– Run the latest SystemVerilog (UVM) simulations
– Work with the verification designer to debug a failing testcase
– Improve a script for automatic register generation
– Push the changes in GIT and tag a new release
– Work with software and RTL designers in the lab to get a device running
– Run some tests to characterize the maximum DMA bandwidth
– Update Redmine with the progress made on current tasks

You have:
– Knowledge of Verilog or VHDL RTL
– Experience with Altera Quartus or Xilinx Vivado tools
– Familiarity with FPGA workflows including RTL design, synthesis, timing closure, prototyping and release
– Expertise in RTL debugging through simulations and in-FPGA logic analyzers
– Familiarity with hardware integration and lab tools

You might also have:
– Expertise in SoC FPGA interconnects such as Avalon or AXI4 interfaces
– Experience with ARM multi-processor systems within an embedded Linux environment
– Knowledge of PCI Express, Ethernet, 10GE, and other protocols

Junior Software Designer (Co-op Placement)

This job might be for you if:
You want your contributions to make a noticeable impact. You love taking on difficult challenges and the satisfaction that comes from finding creative solutions. If you don’t know the answer, you’ll dig until you find it. You play nice with humans and machines. You think on your feet. You like learning new things, and you can learn quickly. You can explain just about anything to anyone. You’re going to take ownership of the time you spend with us and truly make a difference.

A typical day might include:
– Read up on a new standard to understand the system’s desired behavior
– Review a module and add a new feature to it
– Update a design spec
– Work with project management to track progress
– Configure the descriptor chain for an SGDMA to move Audio from Ethernet streams to DDR
– Work with the hardware designer to resolve a FIFO overflow issue
– Test then push your changes into GIT
– Review the latest register definition header file from the RTL designer and update your code
– Work with software and RTL designers in the lab to get a device running
– Update Redmine with the progress made on current tasks

You have:
– Experience with embedded Linux environments
– Knowledge of software design for embedded systems
– Expertise in C/C++
– Performed static code analysis
– Familiarity with hardware integration and lab tools

You might also have:
– Experience with FPGA based embedded systems and ARM processor
– Knowledge of PCI Express, Ethernet, 10GE, and other protocols
– Knowledge of media distribution standards like gStreamer, gPTP, IEEE1722, AVB/AVTP, AES67
– Understanding of DMA engines, SGDMA, high-performance memory

 

Coveloz

Head Office:
232 Herzberg Rd. – Suite 204
Kanata, ON
K2K 2A1
613.410.8559